Integrated circuits in three dimensions allow for the integration of various electronics and systems. Micro-bump technologies are known in the art and may be utilized to increase the density of interconnects in an integrated circuit. Current integrated circuits including micro-bumps and the processes utilized to create the circuits include high thermal processes that may generate cracks, increase the stress, and otherwise damage an integrated circuit. Additionally, high-temperature processes may cause the interdiffusion between various materials associated with the integrated circuit. Additionally, current art micro-bump technology does not provide adequate size and pitch dimensions utilizing the current materials and processes. For example, current processes for forming micro-bumps include solder reflow which laterally extends the bump dimension and makes it difficult to form a bump having a specified size and pitch. There is therefore a need in the art for an integrated circuit and process of forming an integrated circuit in which the micro-bump dimensions are closely controlled for both the size and pitch. There is also a need in the art for an improved integrated circuit and process that does not induce heat stress and other heat-related problems on an integrated circuit.
Current micro-bump technology generally requires the use of special tools and materials that increase the production complexity and cost of forming integrated circuits. Additionally, micro-bump formation processes often require the planarization of the bumps and bonding surface. Such planarization techniques often require additional processes and cost increases as well as pose difficulty in controlling the process parameters. There is a need in the art for an improved process of forming micro-bumps that solves the problems of expensive tools and complex processes.
Additionally, current prior art micro-bump processes generally include an after-bonding underfilling step that is utilized to underfill a gap between wafers. Such after-bonding underfilling is a complex process requiring the control of the viscosity of the underfilling material, which becomes more difficult when a bump height is in the micro scale. There is therefore a need in the art for an improved process that solves the problems associated with underfilling after a bonding process.
Additionally, there is a need in the art for an integrated circuit and process of producing an integrated circuit that utilizes a batch and wafer-level process. This batch and wafer-level fabrication enables mass production and cost reduction as well as decreases the device size and minimizes assembly mismatches.